Paolo Pavan
Welcome to my Home Page
Paolo Pavan
Professor of Electronics
Email: paolo.pavan@unimore.it
web page: [1]
Phones
Office: (+39)-059-205-6158
Fax: (+39)-059-205-6329
Office Hours: by appointment
Curriculum Vitae
Paolo Pavan graduated in Electronics Engineering in 1990 at the University of Padova, where he received his Ph.D. in 1994. From 1992 to 1994 he was graduate student and visiting research engineer at the University of California at Berkeley (U.S.A.). In 1994 he became Research Associate at the University of Modena and Reggio Emilia, Italy and in 1998 Associate Professor of Electronics. Since 2004 he is Full Professor of Electronics at the same University.
His research interests are in the field of electrical characterization and modeling of solid state devices. Presently he is working on characterization and modeling of nonvolatile semiconductor memories. He cooperates with italian and foreign companies for the development of new semiconductor memories.
In 2002 and 2003 he was member of the technical subcommittee "CMOS and Interconnect Reliability" of International Electron Device Meeting (IEDM) and in 2004 he is Chairman of the same Subcommittee, in 2005 he is European Vice-Chair, in 2006 European Chair of the same Meeting. He was chariman of the technical committee in "Nonvolatile and Programmable Device Reliability" subcommittee of ESREF2002. He is guest editor of IEEE Transactions on Device and Material Reliability for the Sept. 2004 Special Isuue "Nonvolatile Memory Reliability". Since 2006 he is member of the Techncal Committee of "International Symposium on VLSI Technology, System and Applications (VLSI-TSA)", Taiwan.
His interests are now also in applied research, in particular in embedded systems, both wireless and on communication bus. He co-founded two spin-off companies working on wireless and "by-wire" embedded systems.
He is responsible of many european and national research projects. He is President of IU.NET (Italian Universities Nano-Electronics Team), a consortium of Universities where research groups are active in nanoelectronics. He published more than 70 papers on international journals and conferences, one book and two book chapters.
RESEARCH
TEACHING
2010-2011
Elettronica C - Corso di Laurea in Ingegneria Elettronica (DM 509/99), 3 anno
Dispositivi Elettronici Avanzati - Corso di Laurea Magistrale in Ingegneria Elettronica (DM 270/04), 2 anno
selected PAPERS and TALKS
1. International Journals
- A. Padovani, L. Larcher, D. Heh, G. Bersuker, V. Della Marca, and P. Pavan, “Temperature Effects on Metal-Alumina-Nitride-Oxide-Silicon Memory Operations,” Applied Physics Letters, vol. 96, no. 23, 7 June 2010.
- G. Betti Beneventi, A. Calderoni, P. Fantini, L. Larcher, P. Pavan, “Analytical model for low-frequency noise in amorphous chalcogenide-based phase-change memory devices”, Journal of Applied Physics, Volume 106(5), Pages 054506 - 054506-8 2009, Sept. 2009.
- D. Brunelli, D. Dondi, A. Bertacchini, L. Larcher, L. Benini, P. Pavan, “Photovoltaic Scavenging Systems: Modeling and Optimization”, Microelectronics Journal, Volume 40, Issue 9, September 2009, Pages 1337-1344.
- L. Larcher, P. Pavan, A. Padovani, G. Ghidini, “A Technique to Extract High-k IPD Stack-Layer Thicknesses From C–V Measurements”, IEEE Electron Device Letters, Vol. 30, N. 6, pp. 653-655, June 2009
- L. Larcher, A. Padovani, P. Pavan, P. Fantini, A. Calderoni, A. Mauri, A Benvenuti, «Modeling nand Flash Memories for IC Design», IEEE Electron Device Letters, Vol. 29, N. 10, pp. 1152 – 1154, Oct. 2008
- A. Padovani, L. Larcher, P. Pavan, “Hole Distributions in NROM Devices: profiling method and effects on reliability,” IEEE Trans. on Electron Devices, Vol. 55, no. 1, pp. 343-349, 2008.
- A. Padovani, L. Larcher, P. Pavan, L. Avital, I. Bloom, B. Eitan, “ID-VGS Based Tools to Profile Charge Distributions on NROMTM Memory Devices,” IEEE Transactions on Device and Materials Reliability, Vol. 7 , no. 1, pp. 97-104, 2007.
- L. Larcher, P. Pavan, B. Eitan, “On the physical mechanism of the NROM memory erase” IEEE Transactions on Electron Devices, Vol. 51, N. 10,Oct. 2004, pp.1593 – 1599.
- L. Larcher, P. Pavan, “Statistical simulations for flash memory reliability analysis and prediction”, IEEE Transactions on Electron Devices, Vol. 51, N. 10, Oct. 2004, pp. 1636- 1643.
- P. Pavan, L. Larcher, M. Cuozzo, P. Zuliani, A. Conte, “A Complete Model for E2PROM Memory Cells for Circuit Simulations,” IEEE Trans. on CAD, Vol. 22, N. 8, August 2003, pp. 1072 –1079.
- L. Larcher, G. Verzellesi, P. Pavan, E. Lusky, I. Bloom, B. Eitan, “Impact of programming charge distribution on threshold voltage and subthreshold slope of NROM memory cells”, IEEE Transactions on Electron Devices, Vol. 49, N. 11, pp. 1939 –1946, Nov. 2002.
- I. Bloom, P. Pavan, B. Eitan, “NROMTM: a new technology for nonvolatile memory products,” Solid State Electronics, Vol. 46, pp. 1757-1763, 2002.
- L. Larcher, S. Bertulu, P. Pavan, “SILC effects on E2PROM memory cell reliability,” IEEE Transactions on Device and Materials Reliability, Vol. 2, N. 1, March 2002, pp. 13 -18
- L. Larcher, P. Pavan, S. Pietri, L. Albani, A. Marmiroli, “A New Compact DC Model of Floating Gate Memory Cells without Capactitive Coupling Coefficients,” IEEE Trans. Electron Devices, Vol. 49, N. 2, pp. 301-307, Feb. 2002.
- I. Bloom, P. Pavan, B. Eitan, “NROMTM – a new non-volatile memory technology: from device to products,” Microelectronics Engineering, Vol. 59, N. 1-4, pp.213-224, Nov. 2001.
- L. Larcher, P. Pavan, L. Albani, T. Ghilardi, D. Cantarelli, A. Marmiroli, “Bias and W/L dependence of capacitive coupling coefficients in Floating Gate Memory cells” IEEE Trans. on Electron Devices, Vol. ED-48(9), pp. 2081-2089, Sept. 2001. - L. Larcher, P. Pavan, F. Pellizzer, G. Ghidini, “A new model of gate capacitance as a simple tool to extract MOS parameters,” IEEE Trans. on Electron Devices, Vol. ED-48(5), pp. 935-945, May 2001.
- B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, D. Finzi, “NROM: a novel localized trapping, 2-bit nonvolatile memory cell,” IEEE Electron Device Letters, Vol. EDL-21(11), pp. 543-545, Nov. 2000.
- L. Vendrame, P. Pavan, G. Corva, A. Nardi, A. Neviani, E. Zanoni, “Degradation mechanisms in polysilicon emitter bipolar junction transistors for digital applications”, introductory invited paper, Microelectronics Reliability, Vol. 40, pp.207-230, 2000.
- A. Neviani, P. Pavan, A. Nardi, A. Chantre, L. Vendrame, E. Zanoni, «Hot-carrier degradation and oxide charge build-up in self-aligned etched-polysilicon npn bipolar transistors», IEEE Trans. Electron Dev., Vol. ED-44 (11), pp.2059-2061, 1997.
- P. Pavan, R. Bez, P. Olivo, E. Zanoni, «Flash Memory Cells - An Overview», Proceedings of IEEE, Vol. 85, N. 8, pp. 1248-1271, Aug. 1997.
- C. Canali, P. Pavan, A. Di Carlo, P. Lugli, R. Malik, M. Manfredi, A. Neviani, L. Vendrame, E. Zanoni, G. Zandler, «Experimental and Monte Carlo analysis of impact-ionization and light emission phenomena in AlGaAs/GaAs HBT's», IEEE Trans. Electron Devices, ED-43 (11), pp. 1796-1777, Nov. 1996.
- P. Pavan, R. Tu, E. Minami, G. Lum, P.K. Ko, C. Hu, «Simulating radiation reliability with BERT», Microelectronics Journal, Vol. 26, No. 6, pp. 627-633, Sept. 1995 (invited paper).
- L. Vendrame, E. Zabotto, A. Dal Fabbro, A. Zanini, E. Zanoni, A. Chantre, and P. Pavan, «Influence of impact-ionization-induced base current reversal on bipolar transistor parameters», IEEE Trans. on Electron Devices, ED-42 (9), pp. 1636-1646, 1995.
- P. Pavan, R. Tu, E. Minami, G. Lum, P.K. Ko, C. Hu, «A complete radiation reliability software simulator», IEEE Trans. on Nuclear Science, pp. 2619-2630, Dec. 1994. - C. Canali, F. Capasso, R. Malik, A. Neviani, P. Pavan, C. Tedesco and E. Zanoni, «Measurement of the electron impact-ionization coefficient at low electric fields in GaAs-based Heterojunction Bipolar Transistors», IEEE Electron Device Letters, EDL-15(9), pp. 354-356, 1994.
- G. Verzellesi, G. Baccarani, C. Canali, P. Pavan, L. Vendrame and E. Zanoni, «Prediction of impact-ionization-induced snap-back in advanced Si n-p-n BJTs by means of a non-local analytical model for the avalanche multiplication factor», IEEE Trans. on Electron Devices, Vol. ED-40 (12), pp. 2296-2300, 1993.
- G. Verzellesi, R. Turetta, P. Pavan, A. Collini, A. Chantre, A. Marty, C. Canali, and E. Zanoni, «Extraction of DC base parasitic resistance of bipolar transistors based on impact-ionization-induced base current reversal», IEEE Electron Device Letters, Vol. EDL-14 (9), pp. 431-434, 1993.
- E. Zanoni, P. Pavan, «Improving reliability and safety of automotive electronics: research activities within the PROMETHEUS project», IEEE MICRO special issue on "Automotive Electronics", Vol. 13 (1), pp. 30-48, 1993, (invited paper).
- E. Zanoni, L. Vendrame, P. Pavan, M. Manfredi, S. Bigliardi, R. Malik, C. Canali «Hot electron induced electroluminescence and impact ionization in AlGaAs/GaAs HBT's», Applied Physics Letters, Vol. 62(4), pp. 402-404, 1993.
- E. Zanoni, E.F. Crabbé, J.M.C. Stork, P. Pavan, G. Verzellesi, L. Vendrame and C.Canali, «Extension of impact-ionization multiplication coefficient measurements to high electric fields in advanced Si BJTs», IEEE Electron Device Letters, vol. EDL-14 (2), pp. 69-71, Febbraio 1993.
- E. Zanoni, R. Malik, J. Nagle, A. Paccagnella, P. Pavan, C. Canali, «Negative base current and impact ionization phenomena in AlGaAs/GaAs HBT's», IEEE Electron Device Letters, Vol. EDL-13 (5), pp. 253-255, 1992.
2. Books and Chapters in Edited Books
[B.3] P. Pavan, L. Larcher, A. Marmiroli, «Floating Gate Devices: Operation and Compact Modeling », Kluwer Academic Publishers, Boston, ISBN 1-4020-7731-9, Feb. 2004.
[B.2] P. Pavan and R. Bez, «The Industry Standard Flash Memory Cell», in Flash Memories, E. Zanoni, P. Olivo, P. Cappelletti, C. Golla Editors, Kluwer Academic Publishers, 1999.
[B.1] G. Verzellesi, P. Pavan, E. Zanoni and C. Canali, «Impact-ionization effects in advanced Si bipolar transistors», in Process and Device Modeling in MADESS, G. Baccarani Editor, Elsevier Science Publishers B.V., pp. 269-324, 1993.
Proposte di Tesi
under construction