https://web.ing.unimo.it/wiki/api.php?action=feedcontributions&feedformat=atom&user=83667Web - User contributions [en]2026-05-04T10:14:55ZUser contributionsMediaWiki 1.39.7https://web.ing.unimo.it/wiki/index.php?title=Luca_Morassi&diff=8879Luca Morassi2012-11-27T09:38:05Z<p>83667: </p>
<hr />
<div>[[File:MyPic.JPG|200px|left]]Ph.D. Student<br />
<br />
Course: Electronics and Telecommunications<br />
<br />
----<br />
Brief CV:<br />
<br />
Luca Morassi was born in Mirandola (Mo), Italy, on September 15th, 1982.<br />
<br />
From July 2008 to February 2009 he was in IMEC (Interuniversity MicroElectronics Centre, Leuven, Belgium) for an internship; during this period he worked on the characterization of High-k-based composed stack for MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) gate oxide. In 2009 he received his academic master degree in Electronic Engineering from University of Modena e Reggio Emilia, Italy - Topic: "Characterization and Simulation of High-k Dielectrics for Innovative Non-Volatile Memories". During 2009 he collaborated with University of Modena and Reggio Emilia with a research activity focused on the electrical characterization of high-k material for Non-Volatile Memory (NVM) devices. Since 2010 he is a PhD student at ICT Electronics & Telecommunications Doctorate School, Modena, Italy with a research activity based on III-V compound semiconductor. His main research field is the characterization of InGaAs-channel MOSFETs and MOSHEMTs (Metal Oxide Semiconductor High Electron Mobilty Transistors) for high power and logic applications.<br />
<br />
<br />
----<br />
<br />
List of publications in journals:<br />
<br />
[J1] Padovani, A.; '''Morassi, L.'''; Raghavan, N.; Larcher, L.; Wenhu Liu; Kin Leong Pey; Bersuker, G.; , "A Physical Model for Post-Breakdown Digital Gate Current Noise," Electron Device Letters, IEEE , vol.31, no.9, pp.1032-1034, Sept. 2010<br />
<br />
[J2] '''Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Injo Ok; Bersuker, G.; , "Interface-Trap Effects in Inversion-Type Enhancement-Mode N-Channel MOSFETs," Electron Devices, IEEE Transactions on , vol.58, no.1, pp.107-114, Jan. 2011<br />
<br />
[J3] Bersuker, G.; Veksler, D.; Young, C.D.; Park, H.; Taylor, W.; Kirsch, P.; Jammy, R.; ''' Morassi, L.'''; Padovani, A.; Larcher, L.; , “Connecting electrical and structural dielectric characteristics,” International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011<br />
<br />
[J4] '''Morassi, L.'''; Verzellesi, G.; Zhao, H.; Lee, J. C.; Veksler, D.; Bersuker, G.; , "Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs," Electron Devices, IEEE Transactions on , vol.59, no.4, pp.1068-1075, April 2012<br />
<br />
[J5] '''Morassi, L.'''; Verzellesi, G.; Zhao, H.; Lee, J. C.; Veksler, D.; Bersuker, G.; , "Engineering Barrier and Buffer Layers in InGaAs Quantum-Well MOSFETs," Electron Devices, IEEE Transactions on , vol.59, no.12, pp.3651-3654, Dec. 2012<br />
----<br />
<br />
List of publications in international conferences:<br />
<br />
[C1] '''Morassi, L.'''; Larcher, L.; Pantisano, L.; Padovani, A.; Degreave, R.; Zahid, M. B.; O'Sullivan, B. J.; , "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing," 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009<br />
<br />
[C2] Bersuker, G.; Heh, D.; Young, C.D.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Yew, K.S.; Ong, Y.C.; Ang, D.S.; Pey, K.L.; Taylor, W.; , "Mechanism of high-k dielectric-induced breakdown of the interfacial SiO2 layer," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.373-378, 2-6 May 2010<br />
<br />
[C3] Bersuker, G.; Veksler, D.; Young, C. D.; Park, H.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Taylor, W.; Kirsch, P. D.; Jammy, R.; , "Connecting electrical and structural dielectric characteristics," Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009<br />
<br />
[C4] '''Morassi, L.'''; Verzellesi, G.; Padovani, A.; Larcher, L.; Pavan, P.; Veksler, D.; Injo Ok; Bersuker, G.; , "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.532-535, 2-6 May 2010<br />
<br />
[C5] ''' Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Ok, I.; Bersuker, G.; , “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010<br />
<br />
[C6] '''Morassi, L.'''; Verzellesi, G.; Pavan, P.; Veksler, D.; Ok, I.; Han Zhao; Lee, J.C.; Bersuker, G.; , "Experimental/numerical investigation of buried-channel InGaA MOS-HEMTs with Al2O3 gate dielectric," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C7] '''Morassi, L.'''; Verzellesi, G.; Larcher, L.; Han Zhao; Lee, J.C.; , "Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C8] '''Morassi, L.'''; Veksler, D.; Bersuker, G.; Verzellesi, G.; , "Generalized High-Low frequency CV technique for interface-trap characterization at III-V/high-k interface," 11th Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC), Porquerolles, France, May 30 - Jun 1, 2012<br />
<br />
[C9] Mohamad Isa, M.; Saguatti, D.; Chini, A.; '''Morassi, L.'''; Verzellesi, G.; Missous, M.;, "Field-Plated InGaAs-InAlAs pHEMTs with 18-V off-state breakdown voltage and 35-GHz fmax," 36th Workshop on Compound Semiconductor Devices and Integrated Circuits (WOCSDICE), Porquerolles, France, May 28-30, 2012<br />
<br />
[C10] Kim, T.-W.; Hill, R. J. W.; Young, C. D.; Veksler, D.; '''Morassi, L.'''; Oktybrshky, S.; Oh, J.; Kang, C.Y.; Kim, D.-H; del Alamo, J. A.; Hobbs, C.; Kirsch, P. D.; Jammy, R.; , "InAs quantum-well MOSFET (Lg = 100 nm) with record high gm, fT and fmax," VLSI Technology (VLSIT), 2012 Symposium on , vol., no., pp.179-180, 12-14 June 2012<br />
<br />
[C11] '''Morassi, L.'''; Veksler, D.; Bersuker, G.; Verzellesi, G.; , " Interface-trap characterization at III-V/high-k interface: a fast and generalized method based on High-Low frequency CV," 21st European Workshop on Heterostructure Technology (HETECH), Barcelona, Spain, Nov 5-7, 2012<br />
----<br />
<br />
Scientific activities:<br />
<br />
Participation at the conference: IEEE International Reliability Physics Symposium (IRPS 2010); presentation of the work [C4]. <br />
<br />
Participation at the conference: European Workshop on Heterostructure Technology (HETECH 2010); presentation of the work [C5]. <br />
<br />
Participation at the conference: 23rd International Conference on Indium Phosphide and Related Materials (IPRM 2011): presentation of the works [C6] and [C7].<br />
<br />
Participation at the conference: 11th Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC): presentation of the works [C8].<br />
<br />
<br />
----<br />
<br />
DISMI - Dipartimento di Scienze e Metodi dell'Ingegneria<br />
<br />
Università di Modena e Reggio Emilia<br />
<br />
Pad. Tamburini - Via Amendola 2<br />
<br />
42122, Reggio Emilia<br />
<br />
<br />
mail: luca.morassi@unimore.it<br />
<br />
Tel: +39-0522522638<br />
<br />
Fax: +39-0522522609<br />
<br />
Cell: +39-3381468756</div>83667https://web.ing.unimo.it/wiki/index.php?title=Luca_Morassi&diff=8719Luca Morassi2012-07-23T10:32:25Z<p>83667: </p>
<hr />
<div>[[File:MyPic.JPG|200px|left]]Ph.D. Student<br />
<br />
Course: Electronics and Telecommunications<br />
<br />
----<br />
Brief CV:<br />
<br />
Luca Morassi was born in Mirandola (Mo), Italy, on September 15th, 1982.<br />
<br />
From July 2008 to February 2009 he was in IMEC (Interuniversity MicroElectronics Centre, Leuven, Belgium) for an internship; during this period he worked on the characterization of High-k-based composed stack for MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) gate oxide. In 2009 he received his academic master degree in Electronic Engineering from University of Modena e Reggio Emilia, Italy - Topic: "Characterization and Simulation of High-k Dielectrics for Innovative Non-Volatile Memories". During 2009 he collaborated with University of Modena and Reggio Emilia with a research activity focused on the electrical characterization of high-k material for Non-Volatile Memory (NVM) devices. Since 2010 he is a PhD student at ICT Electronics & Telecommunications Doctorate School, Modena, Italy with a research activity based on III-V compound semiconductor. His main research field is the characterization of InGaAs-channel MOSFETs and MOSHEMTs (Metal Oxide Semiconductor High Electron Mobilty Transistors) for high power and logic applications.<br />
<br />
<br />
----<br />
<br />
List of publications in journals:<br />
<br />
[J1] Padovani, A.; '''Morassi, L.'''; Raghavan, N.; Larcher, L.; Wenhu Liu; Kin Leong Pey; Bersuker, G.; , "A Physical Model for Post-Breakdown Digital Gate Current Noise," Electron Device Letters, IEEE , vol.31, no.9, pp.1032-1034, Sept. 2010<br />
<br />
[J2] '''Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Injo Ok; Bersuker, G.; , "Interface-Trap Effects in Inversion-Type Enhancement-Mode N-Channel MOSFETs," Electron Devices, IEEE Transactions on , vol.58, no.1, pp.107-114, Jan. 2011<br />
<br />
[J3] Bersuker, G.; Veksler, D.; Young, C.D.; Park, H.; Taylor, W.; Kirsch, P.; Jammy, R.; ''' Morassi, L.'''; Padovani, A.; Larcher, L.; , “Connecting electrical and structural dielectric characteristics,” International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011<br />
<br />
[J4] '''Morassi, L.'''; Verzellesi, G.; Zhao, H.; Lee, J. C.; Veksler, D.; Bersuker, G.; , "Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs," Electron Devices, IEEE Transactions on , vol.59, no.4, pp.1068-1075, April 2012<br />
<br />
<br />
----<br />
<br />
List of publications in international conferences:<br />
<br />
[C1] '''Morassi, L.'''; Larcher, L.; Pantisano, L.; Padovani, A.; Degreave, R.; Zahid, M. B.; O'Sullivan, B. J.; , "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing," 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009<br />
<br />
[C2] Bersuker, G.; Heh, D.; Young, C.D.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Yew, K.S.; Ong, Y.C.; Ang, D.S.; Pey, K.L.; Taylor, W.; , "Mechanism of high-k dielectric-induced breakdown of the interfacial SiO2 layer," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.373-378, 2-6 May 2010<br />
<br />
[C3] Bersuker, G.; Veksler, D.; Young, C. D.; Park, H.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Taylor, W.; Kirsch, P. D.; Jammy, R.; , "Connecting electrical and structural dielectric characteristics," Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009<br />
<br />
[C4] '''Morassi, L.'''; Verzellesi, G.; Padovani, A.; Larcher, L.; Pavan, P.; Veksler, D.; Injo Ok; Bersuker, G.; , "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.532-535, 2-6 May 2010<br />
<br />
[C5] ''' Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Ok, I.; Bersuker, G.; , “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010<br />
<br />
[C6] '''Morassi, L.'''; Verzellesi, G.; Pavan, P.; Veksler, D.; Ok, I.; Han Zhao; Lee, J.C.; Bersuker, G.; , "Experimental/numerical investigation of buried-channel InGaA MOS-HEMTs with Al2O3 gate dielectric," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C7] '''Morassi, L.'''; Verzellesi, G.; Larcher, L.; Han Zhao; Lee, J.C.; , "Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C8] '''Morassi, L.'''; Veksler, D.; Bersuker, G.; Verzellesi, G.; , "Generalized High-Low frequency CV technique for interface-trap characterization at III-V/high-k interface," 11th Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC), Porquerolles, France, May 30 - Jun 1, 2012<br />
<br />
[C9] Mohamad Isa, M.; Saguatti, D.; Chini, A.; '''Morassi, L.'''; Verzellesi, G.; Missous, M.;, "Field-Plated InGaAs-InAlAs pHEMTs with 18-V off-state breakdown voltage and 35-GHz fmax," 36th Workshop on Compound Semiconductor Devices and Integrated Circuits (WOCSDICE), Porquerolles, France, May 28-30, 2012<br />
<br />
[C10] Kim, T.-W.; Hill, R. J. W.; Young, C. D.; Veksler, D.; '''Morassi, L.'''; Oktybrshky, S.; Oh, J.; Kang, C.Y.; Kim, D.-H; del Alamo, J. A.; Hobbs, C.; Kirsch, P. D.; Jammy, R.; , "InAs quantum-well MOSFET (Lg = 100 nm) with record high gm, fT and fmax," VLSI Technology (VLSIT), 2012 Symposium on , vol., no., pp.179-180, 12-14 June 2012<br />
<br />
<br />
----<br />
<br />
Scientific activities:<br />
<br />
Participation at the conference: IEEE International Reliability Physics Symposium (IRPS 2010); presentation of the work [C4]. <br />
<br />
Participation at the conference: European Workshop on Heterostructure Technology (HETECH 2010); presentation of the work [C5]. <br />
<br />
Participation at the conference: 23rd International Conference on Indium Phosphide and Related Materials (IPRM 2011): presentation of the works [C6] and [C7].<br />
<br />
Participation at the conference: 11th Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC): presentation of the works [C8].<br />
<br />
<br />
----<br />
<br />
DISMI - Dipartimento di Scienze e Metodi dell'Ingegneria<br />
<br />
Università di Modena e Reggio Emilia<br />
<br />
Pad. Tamburini - Via Amendola 2<br />
<br />
42122, Reggio Emilia<br />
<br />
<br />
mail: luca.morassi@unimore.it<br />
<br />
Tel: +39-0522522638<br />
<br />
Fax: +39-0522522609<br />
<br />
Cell: +39-3381468756</div>83667https://web.ing.unimo.it/wiki/index.php?title=Luca_Morassi&diff=8688Luca Morassi2012-07-05T08:53:24Z<p>83667: </p>
<hr />
<div>[[File:MyPic.JPG|200px|left]]Ph.D. Student<br />
<br />
Course: Electronics and Telecommunications<br />
<br />
----<br />
Brief CV:<br />
<br />
Luca Morassi was born in Mirandola (Mo), Italy, on September 15th, 1982.<br />
<br />
From July 2008 to February 2009 he was in IMEC (Interuniversity MicroElectronics Centre, Leuven, Belgium) for an internship; during this period he worked on the characterization of High-k-based composed stack for MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) gate oxide. In 2009 he received his academic master degree in Electronic Engineering from University of Modena e Reggio Emilia, Italy - Topic: "Characterization and Simulation of High-k Dielectrics for Innovative Non-Volatile Memories". During 2009 he collaborated with University of Modena and Reggio Emilia with a research activity focused on the electrical characterization of high-k material for Non-Volatile Memory (NVM) devices. Since 2010 he is a PhD student at ICT Electronics & Telecommunications Doctorate School, Modena, Italy with a research activity based on III-V compound semiconductor. His main research field is the characterization of InGaAs-channel MOSFETs and MOSHEMTs (Metal Oxide Semiconductor High Electron Mobilty Transistors) for high power and logic applications.<br />
<br />
<br />
----<br />
<br />
List of publications in journals:<br />
<br />
[J1] Padovani, A.; '''Morassi, L.'''; Raghavan, N.; Larcher, L.; Wenhu Liu; Kin Leong Pey; Bersuker, G.; , "A Physical Model for Post-Breakdown Digital Gate Current Noise," Electron Device Letters, IEEE , vol.31, no.9, pp.1032-1034, Sept. 2010<br />
<br />
[J2] '''Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Injo Ok; Bersuker, G.; , "Interface-Trap Effects in Inversion-Type Enhancement-Mode N-Channel MOSFETs," Electron Devices, IEEE Transactions on , vol.58, no.1, pp.107-114, Jan. 2011<br />
<br />
[J3] Bersuker, G.; Veksler, D.; Young, C.D.; Park, H.; Taylor, W.; Kirsch, P.; Jammy, R.; ''' Morassi, L.'''; Padovani, A.; Larcher, L.; , “Connecting electrical and structural dielectric characteristics,” International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011<br />
<br />
[J4] '''Morassi, L.'''; Verzellesi, G.; Zhao, H.; Lee, J. C.; Veksler, D.; Bersuker, G.; , "Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs," Electron Devices, IEEE Transactions on , vol.59, no.4, pp.1068-1075, April 2012<br />
<br />
<br />
----<br />
<br />
List of publications in international conferences:<br />
<br />
[C1] '''Morassi, L.'''; Larcher, L.; Pantisano, L.; Padovani, A.; Degreave, R.; Zahid, M. B.; O'Sullivan, B. J.; , "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing," 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009<br />
<br />
[C2] Bersuker, G.; Heh, D.; Young, C.D.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Yew, K.S.; Ong, Y.C.; Ang, D.S.; Pey, K.L.; Taylor, W.; , "Mechanism of high-k dielectric-induced breakdown of the interfacial SiO2 layer," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.373-378, 2-6 May 2010<br />
<br />
[C3] Bersuker, G.; Veksler, D.; Young, C. D.; Park, H.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Taylor, W.; Kirsch, P. D.; Jammy, R.; , "Connecting electrical and structural dielectric characteristics," Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009<br />
<br />
[C4] '''Morassi, L.'''; Verzellesi, G.; Padovani, A.; Larcher, L.; Pavan, P.; Veksler, D.; Injo Ok; Bersuker, G.; , "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.532-535, 2-6 May 2010<br />
<br />
[C5] ''' Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Ok, I.; Bersuker, G.; , “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010<br />
<br />
[C6] '''Morassi, L.'''; Verzellesi, G.; Pavan, P.; Veksler, D.; Ok, I.; Han Zhao; Lee, J.C.; Bersuker, G.; , "Experimental/numerical investigation of buried-channel InGaA MOS-HEMTs with Al2O3 gate dielectric," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C7] '''Morassi, L.'''; Verzellesi, G.; Larcher, L.; Han Zhao; Lee, J.C.; , "Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C8] '''Morassi, L.'''; Veksler, D.; Bersuker, G.; Verzellesi, G.; , "Generalized High-Low frequency CV technique for interface-trap characterization at III-V/high-k interface," 11th Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC), Porquerolles, France, May 30 - Jun 1, 2012<br />
<br />
[C9] Mohamad Isa, M.; Saguatti, D.; Chini, A.; '''Morassi, L.'''; Verzellesi, G.; Missous, M.;, "Field-Plated InGaAs-InAlAs pHEMTs with 18-V off-state breakdown voltage and 35-GHz fmax," 36th Workshop on Compound Semiconductor Devices and Integrated Circuits (WOCSDICE), Porquerolles, France, May 28-30, 2012<br />
<br />
<br />
----<br />
<br />
Scientific activities:<br />
<br />
Participation at the conference: IEEE International Reliability Physics Symposium (IRPS 2010); presentation of the work [C4]. <br />
<br />
Participation at the conference: European Workshop on Heterostructure Technology (HETECH 2010); presentation of the work [C5]. <br />
<br />
Participation at the conference: 23rd International Conference on Indium Phosphide and Related Materials (IPRM 2011): presentation of the works [C6] and [C7].<br />
<br />
Participation at the conference: 11th Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC): presentation of the works [C8].<br />
<br />
<br />
----<br />
<br />
DISMI - Dipartimento di Scienze e Metodi dell'Ingegneria<br />
<br />
Università di Modena e Reggio Emilia<br />
<br />
Pad. Tamburini - Via Amendola 2<br />
<br />
42122, Reggio Emilia<br />
<br />
<br />
mail: luca.morassi@unimore.it<br />
<br />
Tel: +39-0522522638<br />
<br />
Fax: +39-0522522609<br />
<br />
Cell: +39-3381468756</div>83667https://web.ing.unimo.it/wiki/index.php?title=Luca_Morassi&diff=8687Luca Morassi2012-07-05T08:53:06Z<p>83667: </p>
<hr />
<div>[[File:MyPic.JPG|200px|left]]Ph.D. Student<br />
<br />
Course: Electronics and Telecommunications<br />
<br />
----<br />
Brief CV:<br />
<br />
Luca Morassi was born in Mirandola (Mo), Italy, on September 15th, 1982.<br />
<br />
From July 2008 to February 2009 he was in IMEC (Interuniversity MicroElectronics Centre, Leuven, Belgium) for an internship; during this period he worked on the characterization of High-k-based composed stack for MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) gate oxide. In 2009 he received his academic master degree in Electronic Engineering from University of Modena e Reggio Emilia, Italy - Topic: "Characterization and Simulation of High-k Dielectrics for Innovative Non-Volatile Memories". During 2009 he collaborated with University of Modena and Reggio Emilia with a research activity focused on the electrical characterization of high-k material for Non-Volatile Memory (NVM) devices. Since 2010 he is a PhD student at ICT Electronics & Telecommunications Doctorate School, Modena, Italy with a research activity based on III-V compound semiconductor. His main research field is the characterization of InGaAs-channel MOSFETs and MOSHEMTs (Metal Oxide Semiconductor High Electron Mobilty Transistors) for high power and logic applications.<br />
<br />
<br />
----<br />
<br />
List of publications in journals:<br />
<br />
[J1] Padovani, A.; '''Morassi, L.'''; Raghavan, N.; Larcher, L.; Wenhu Liu; Kin Leong Pey; Bersuker, G.; , "A Physical Model for Post-Breakdown Digital Gate Current Noise," Electron Device Letters, IEEE , vol.31, no.9, pp.1032-1034, Sept. 2010<br />
<br />
[J2] '''Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Injo Ok; Bersuker, G.; , "Interface-Trap Effects in Inversion-Type Enhancement-Mode N-Channel MOSFETs," Electron Devices, IEEE Transactions on , vol.58, no.1, pp.107-114, Jan. 2011<br />
<br />
[J3] Bersuker, G.; Veksler, D.; Young, C.D.; Park, H.; Taylor, W.; Kirsch, P.; Jammy, R.; ''' Morassi, L.'''; Padovani, A.; Larcher, L.; , “Connecting electrical and structural dielectric characteristics,” International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011<br />
<br />
[J4] '''Morassi, L.'''; Verzellesi, G.; Zhao, H.; Lee, J. C.; Veksler, D.; Bersuker, G.; , "Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs," Electron Devices, IEEE Transactions on , vol.59, no.4, pp.1068-1075, April 2012<br />
<br />
<br />
----<br />
<br />
List of publications in international conferences:<br />
<br />
[C1] '''Morassi, L.'''; Larcher, L.; Pantisano, L.; Padovani, A.; Degreave, R.; Zahid, M. B.; O'Sullivan, B. J.; , "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing," 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009<br />
<br />
[C2] Bersuker, G.; Heh, D.; Young, C.D.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Yew, K.S.; Ong, Y.C.; Ang, D.S.; Pey, K.L.; Taylor, W.; , "Mechanism of high-k dielectric-induced breakdown of the interfacial SiO2 layer," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.373-378, 2-6 May 2010<br />
<br />
[C3] Bersuker, G.; Veksler, D.; Young, C. D.; Park, H.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Taylor, W.; Kirsch, P. D.; Jammy, R.; , "Connecting electrical and structural dielectric characteristics," Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009<br />
<br />
[C4] '''Morassi, L.'''; Verzellesi, G.; Padovani, A.; Larcher, L.; Pavan, P.; Veksler, D.; Injo Ok; Bersuker, G.; , "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.532-535, 2-6 May 2010<br />
<br />
[C5] ''' Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Ok, I.; Bersuker, G.; , “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010<br />
<br />
[C6] '''Morassi, L.'''; Verzellesi, G.; Pavan, P.; Veksler, D.; Ok, I.; Han Zhao; Lee, J.C.; Bersuker, G.; , "Experimental/numerical investigation of buried-channel InGaA MOS-HEMTs with Al2O3 gate dielectric," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C7] '''Morassi, L.'''; Verzellesi, G.; Larcher, L.; Han Zhao; Lee, J.C.; , "Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C8] '''Morassi, L.'''; Veksler, D.; Bersuker, G.; Verzellesi, G.; , "Generalized High-Low frequency CV technique for interface-trap characterization at III-V/high-k interface," 11th Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC), Porquerolles, France, May 30 - Jun 1, 2012<br />
<br />
[C9] Mohamad Isa, M.; Saguatti, D.; Chini, A.; '''Morassi, L.'''; Verzellesi, G.; Missous, M.;, "Field-Plated InGaAs-InAlAs pHEMTs with 18-V off-state breakdown voltage and 35-GHz fmax," 36th Workshop on Compound Semiconductor Devices and Integrated Circuits (WOCSDICE), Porquerolles, France, May 28-30, 2012<br />
<br />
<br />
----<br />
<br />
<br />
Scientific activities:<br />
<br />
Participation at the conference: IEEE International Reliability Physics Symposium (IRPS 2010); presentation of the work [C4]. <br />
<br />
Participation at the conference: European Workshop on Heterostructure Technology (HETECH 2010); presentation of the work [C5]. <br />
<br />
Participation at the conference: 23rd International Conference on Indium Phosphide and Related Materials (IPRM 2011): presentation of the works [C6] and [C7].<br />
<br />
Participation at the conference: 11th Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC): presentation of the works [C8].<br />
<br />
----<br />
<br />
DISMI - Dipartimento di Scienze e Metodi dell'Ingegneria<br />
<br />
Università di Modena e Reggio Emilia<br />
<br />
Pad. Tamburini - Via Amendola 2<br />
<br />
42122, Reggio Emilia<br />
<br />
<br />
mail: luca.morassi@unimore.it<br />
<br />
Tel: +39-0522522638<br />
<br />
Fax: +39-0522522609<br />
<br />
Cell: +39-3381468756</div>83667https://web.ing.unimo.it/wiki/index.php?title=Luca_Morassi&diff=8686Luca Morassi2012-07-05T08:52:36Z<p>83667: </p>
<hr />
<div>[[File:MyPic.JPG|200px|left]]Ph.D. Student<br />
<br />
Course: Electronics and Telecommunications<br />
<br />
----<br />
Brief CV:<br />
<br />
Luca Morassi was born in Mirandola (Mo), Italy, on September 15th, 1982.<br />
<br />
From July 2008 to February 2009 he was in IMEC (Interuniversity MicroElectronics Centre, Leuven, Belgium) for an internship; during this period he worked on the characterization of High-k-based composed stack for MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) gate oxide. In 2009 he received his academic master degree in Electronic Engineering from University of Modena e Reggio Emilia, Italy - Topic: "Characterization and Simulation of High-k Dielectrics for Innovative Non-Volatile Memories". During 2009 he collaborated with University of Modena and Reggio Emilia with a research activity focused on the electrical characterization of high-k material for Non-Volatile Memory (NVM) devices. Since 2010 he is a PhD student at ICT Electronics & Telecommunications Doctorate School, Modena, Italy with a research activity based on III-V compound semiconductor. His main research field is the characterization of InGaAs-channel MOSFETs and MOSHEMTs (Metal Oxide Semiconductor High Electron Mobilty Transistors) for high power and logic applications.<br />
<br />
<br />
----<br />
<br />
List of publications in journals:<br />
<br />
[J1] Padovani, A.; '''Morassi, L.'''; Raghavan, N.; Larcher, L.; Wenhu Liu; Kin Leong Pey; Bersuker, G.; , "A Physical Model for Post-Breakdown Digital Gate Current Noise," Electron Device Letters, IEEE , vol.31, no.9, pp.1032-1034, Sept. 2010<br />
<br />
[J2] '''Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Injo Ok; Bersuker, G.; , "Interface-Trap Effects in Inversion-Type Enhancement-Mode N-Channel MOSFETs," Electron Devices, IEEE Transactions on , vol.58, no.1, pp.107-114, Jan. 2011<br />
<br />
[J3] Bersuker, G.; Veksler, D.; Young, C.D.; Park, H.; Taylor, W.; Kirsch, P.; Jammy, R.; ''' Morassi, L.'''; Padovani, A.; Larcher, L.; , “Connecting electrical and structural dielectric characteristics,” International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011<br />
<br />
[J4] '''Morassi, L.'''; Verzellesi, G.; Zhao, H.; Lee, J. C.; Veksler, D.; Bersuker, G.; , "Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs," Electron Devices, IEEE Transactions on , vol.59, no.4, pp.1068-1075, April 2012<br />
<br />
<br />
----<br />
<br />
List of publications in international conferences:<br />
<br />
[C1] '''Morassi, L.'''; Larcher, L.; Pantisano, L.; Padovani, A.; Degreave, R.; Zahid, M. B.; O'Sullivan, B. J.; , "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing," 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009<br />
<br />
[C2] Bersuker, G.; Heh, D.; Young, C.D.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Yew, K.S.; Ong, Y.C.; Ang, D.S.; Pey, K.L.; Taylor, W.; , "Mechanism of high-k dielectric-induced breakdown of the interfacial SiO2 layer," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.373-378, 2-6 May 2010<br />
<br />
[C3] Bersuker, G.; Veksler, D.; Young, C. D.; Park, H.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Taylor, W.; Kirsch, P. D.; Jammy, R.; , "Connecting electrical and structural dielectric characteristics," Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009<br />
<br />
[C4] '''Morassi, L.'''; Verzellesi, G.; Padovani, A.; Larcher, L.; Pavan, P.; Veksler, D.; Injo Ok; Bersuker, G.; , "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.532-535, 2-6 May 2010<br />
<br />
[C5] ''' Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Ok, I.; Bersuker, G.; , “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010<br />
<br />
[C6] '''Morassi, L.'''; Verzellesi, G.; Pavan, P.; Veksler, D.; Ok, I.; Han Zhao; Lee, J.C.; Bersuker, G.; , "Experimental/numerical investigation of buried-channel InGaA MOS-HEMTs with Al2O3 gate dielectric," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C7] '''Morassi, L.'''; Verzellesi, G.; Larcher, L.; Han Zhao; Lee, J.C.; , "Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C8] '''Morassi, L.'''; Veksler, D.; Bersuker, G.; Verzellesi, G.; , "Generalized High-Low frequency CV technique for interface-trap characterization at III-V/high-k interface," 11th Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC), Porquerolles, France, May 30 - Jun 1, 2012<br />
<br />
[C9] Mohamad Isa, M.; Saguatti, D.; Chini, A.; '''Morassi, L.'''; Verzellesi, G.; Missous, M.;, "Field-Plated InGaAs-InAlAs pHEMTs with 18-V off-state breakdown voltage and 35-GHz fmax," 36th Workshop on Compound Semiconductor Devices and Integrated Circuits (WOCSDICE), Porquerolles, France, May 28-30, 2012<br />
<br />
----<br />
<br />
Scientific activities:<br />
<br />
Participation at the conference: IEEE International Reliability Physics Symposium (IRPS 2010); presentation of the work [C4]. <br />
<br />
Participation at the conference: European Workshop on Heterostructure Technology (HETECH 2010); presentation of the work [C5]. <br />
<br />
Participation at the conference: 23rd International Conference on Indium Phosphide and Related Materials (IPRM 2011): presentation of the works [C6] and [C7].<br />
<br />
Participation at the conference: 11th Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC): presentation of the works [C8].<br />
<br />
----<br />
<br />
DISMI - Dipartimento di Scienze e Metodi dell'Ingegneria<br />
<br />
Università di Modena e Reggio Emilia<br />
<br />
Pad. Tamburini - Via Amendola 2<br />
<br />
42122, Reggio Emilia<br />
<br />
<br />
mail: luca.morassi@unimore.it<br />
<br />
Tel: +39-0522522638<br />
<br />
Fax: +39-0522522609<br />
<br />
Cell: +39-3381468756</div>83667https://web.ing.unimo.it/wiki/index.php?title=Luca_Morassi&diff=8685Luca Morassi2012-07-05T08:52:07Z<p>83667: </p>
<hr />
<div>[[File:MyPic.JPG|200px|left]]Ph.D. Student<br />
<br />
Course: Electronics and Telecommunications<br />
<br />
----<br />
Brief CV:<br />
<br />
Luca Morassi was born in Mirandola (Mo), Italy, on September 15th, 1982.<br />
<br />
From July 2008 to February 2009 he was in IMEC (Interuniversity MicroElectronics Centre, Leuven, Belgium) for an internship; during this period he worked on the characterization of High-k-based composed stack for MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) gate oxide. In 2009 he received his academic master degree in Electronic Engineering from University of Modena e Reggio Emilia, Italy - Topic: "Characterization and Simulation of High-k Dielectrics for Innovative Non-Volatile Memories". During 2009 he collaborated with University of Modena and Reggio Emilia with a research activity focused on the electrical characterization of high-k material for Non-Volatile Memory (NVM) devices. Since 2010 he is a PhD student at ICT Electronics & Telecommunications Doctorate School, Modena, Italy with a research activity based on III-V compound semiconductor. His main research field is the characterization of InGaAs-channel MOSFETs and MOSHEMTs (Metal Oxide Semiconductor High Electron Mobilty Transistors) for high power and logic applications.<br />
<br />
<br />
----<br />
<br />
List of publications in journals:<br />
<br />
[J1] Padovani, A.; '''Morassi, L.'''; Raghavan, N.; Larcher, L.; Wenhu Liu; Kin Leong Pey; Bersuker, G.; , "A Physical Model for Post-Breakdown Digital Gate Current Noise," Electron Device Letters, IEEE , vol.31, no.9, pp.1032-1034, Sept. 2010<br />
<br />
[J2] '''Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Injo Ok; Bersuker, G.; , "Interface-Trap Effects in Inversion-Type Enhancement-Mode N-Channel MOSFETs," Electron Devices, IEEE Transactions on , vol.58, no.1, pp.107-114, Jan. 2011<br />
<br />
[J3] Bersuker, G.; Veksler, D.; Young, C.D.; Park, H.; Taylor, W.; Kirsch, P.; Jammy, R.; ''' Morassi, L.'''; Padovani, A.; Larcher, L.; , “Connecting electrical and structural dielectric characteristics,” International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011<br />
<br />
[J4] '''Morassi, L.'''; Verzellesi, G.; Zhao, H.; Lee, J. C.; Veksler, D.; Bersuker, G.; , "Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs," Electron Devices, IEEE Transactions on , vol.59, no.4, pp.1068-1075, April 2012<br />
<br />
<br />
----<br />
<br />
List of publications in international conferences:<br />
<br />
[C1] '''Morassi, L.'''; Larcher, L.; Pantisano, L.; Padovani, A.; Degreave, R.; Zahid, M. B.; O'Sullivan, B. J.; , "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing," 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009<br />
<br />
[C2] Bersuker, G.; Heh, D.; Young, C.D.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Yew, K.S.; Ong, Y.C.; Ang, D.S.; Pey, K.L.; Taylor, W.; , "Mechanism of high-k dielectric-induced breakdown of the interfacial SiO2 layer," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.373-378, 2-6 May 2010<br />
<br />
[C3] Bersuker, G.; Veksler, D.; Young, C. D.; Park, H.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Taylor, W.; Kirsch, P. D.; Jammy, R.; , "Connecting electrical and structural dielectric characteristics," Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009<br />
<br />
[C4] '''Morassi, L.'''; Verzellesi, G.; Padovani, A.; Larcher, L.; Pavan, P.; Veksler, D.; Injo Ok; Bersuker, G.; , "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.532-535, 2-6 May 2010<br />
<br />
[C5] ''' Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Ok, I.; Bersuker, G.; , “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010<br />
<br />
[C6] '''Morassi, L.'''; Verzellesi, G.; Pavan, P.; Veksler, D.; Ok, I.; Han Zhao; Lee, J.C.; Bersuker, G.; , "Experimental/numerical investigation of buried-channel InGaA MOS-HEMTs with Al2O3 gate dielectric," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C7] '''Morassi, L.'''; Verzellesi, G.; Larcher, L.; Han Zhao; Lee, J.C.; , "Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C8] '''Morassi, L.'''; Veksler, D.; Bersuker, G.; Verzellesi, G.; , "Generalized High-Low frequency CV technique for interface-trap characterization at III-V/high-k interface," 11th Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC), Porquerolles, France, May 30 - Jun 1, 2012<br />
<br />
[C9] Mohamad Isa, M.; Saguatti, D.; Chini, A.; '''Morassi, L.'''; Verzellesi, G.; Missous, M.;, "Field-Plated InGaAs-InAlAs pHEMTs with 18-V off-state breakdown voltage and 35-GHz fmax," 36th Workshop on Compound Semiconductor Devices and Integrated Circuits (WOCSDICE), Porquerolles, France, May 28-30, 2012<br />
----<br />
<br />
Scientific activities:<br />
<br />
Participation at the conference: IEEE International Reliability Physics Symposium (IRPS 2010); presentation of the work [C4]. <br />
<br />
Participation at the conference: European Workshop on Heterostructure Technology (HETECH 2010); presentation of the work [C5]. <br />
<br />
Participation at the conference: 23rd International Conference on Indium Phosphide and Related Materials (IPRM 2011): presentation of the works [C6] and [C7].<br />
<br />
Participation at the conference: 11th Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC): presentation of the works [C8].<br />
<br />
----<br />
<br />
DISMI - Dipartimento di Scienze e Metodi dell'Ingegneria<br />
<br />
Università di Modena e Reggio Emilia<br />
<br />
Pad. Tamburini - Via Amendola 2<br />
<br />
42122, Reggio Emilia<br />
<br />
<br />
mail: luca.morassi@unimore.it<br />
<br />
Tel: +39-0522522638<br />
<br />
Fax: +39-0522522609<br />
<br />
Cell: +39-3381468756</div>83667https://web.ing.unimo.it/wiki/index.php?title=Luca_Morassi&diff=8558Luca Morassi2012-03-28T10:52:06Z<p>83667: </p>
<hr />
<div>[[File:MyPic.JPG|200px|left]]Ph.D. Student<br />
<br />
Course: Electronics and Telecommunications<br />
<br />
----<br />
Brief CV:<br />
<br />
Luca Morassi was born in Mirandola (Mo), Italy, on September 15th, 1982.<br />
<br />
From July 2008 to February 2009 he was in IMEC (Interuniversity MicroElectronics Centre, Leuven, Belgium) for an internship; during this period he worked on the characterization of High-k-based composed stack for MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) gate oxide. In 2009 he received his academic master degree in Electronic Engineering from University of Modena e Reggio Emilia, Italy - Topic: "Characterization and Simulation of High-k Dielectrics for Innovative Non-Volatile Memories". During 2009 he collaborated with University of Modena and Reggio Emilia with a research activity focused on the electrical characterization of high-k material for Non-Volatile Memory (NVM) devices. Since 2010 he is a PhD student at ICT Electronics & Telecommunications Doctorate School, Modena, Italy with a research activity based on III-V compound semiconductor. His main research field is the characterization of InGaAs-channel MOSFETs and MOSHEMTs (Metal Oxide Semiconductor High Electron Mobilty Transistors) for high power and logic applications.<br />
<br />
<br />
----<br />
<br />
List of publications in journals:<br />
<br />
[J1] Padovani, A.; '''Morassi, L.'''; Raghavan, N.; Larcher, L.; Wenhu Liu; Kin Leong Pey; Bersuker, G.; , "A Physical Model for Post-Breakdown Digital Gate Current Noise," Electron Device Letters, IEEE , vol.31, no.9, pp.1032-1034, Sept. 2010<br />
<br />
[J2] '''Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Injo Ok; Bersuker, G.; , "Interface-Trap Effects in Inversion-Type Enhancement-Mode N-Channel MOSFETs," Electron Devices, IEEE Transactions on , vol.58, no.1, pp.107-114, Jan. 2011<br />
<br />
[J3] Bersuker, G.; Veksler, D.; Young, C.D.; Park, H.; Taylor, W.; Kirsch, P.; Jammy, R.; ''' Morassi, L.'''; Padovani, A.; Larcher, L.; , “Connecting electrical and structural dielectric characteristics,” International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011<br />
<br />
[J4] '''Morassi, L.'''; Verzellesi, G.; Zhao, H.; Lee, J. C.; Veksler, D.; Bersuker, G.; , "Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs," Electron Devices, IEEE Transactions on , vol.59, no.4, pp.1068-1075, April 2012<br />
<br />
<br />
----<br />
<br />
List of publications in international conferences:<br />
<br />
[C1] '''Morassi, L.'''; Larcher, L.; Pantisano, L.; Padovani, A.; Degreave, R.; Zahid, M. B.; O'Sullivan, B. J.; , "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing," 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009<br />
<br />
[C2] Bersuker, G.; Heh, D.; Young, C.D.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Yew, K.S.; Ong, Y.C.; Ang, D.S.; Pey, K.L.; Taylor, W.; , "Mechanism of high-k dielectric-induced breakdown of the interfacial SiO2 layer," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.373-378, 2-6 May 2010<br />
<br />
[C3] Bersuker, G.; Veksler, D.; Young, C. D.; Park, H.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Taylor, W.; Kirsch, P. D.; Jammy, R.; , "Connecting electrical and structural dielectric characteristics," Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009<br />
<br />
[C4] '''Morassi, L.'''; Verzellesi, G.; Padovani, A.; Larcher, L.; Pavan, P.; Veksler, D.; Injo Ok; Bersuker, G.; , "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.532-535, 2-6 May 2010<br />
<br />
[C5] ''' Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Ok, I.; Bersuker, G.; , “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010<br />
<br />
[C6] '''Morassi, L.'''; Verzellesi, G.; Pavan, P.; Veksler, D.; Ok, I.; Han Zhao; Lee, J.C.; Bersuker, G.; , "Experimental/numerical investigation of buried-channel InGaA MOS-HEMTs with Al2O3 gate dielectric," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C7] '''Morassi, L.'''; Verzellesi, G.; Larcher, L.; Han Zhao; Lee, J.C.; , "Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
<br />
----<br />
<br />
Scientific activities:<br />
<br />
Participation at the conference: IEEE International Reliability Physics Symposium (IRPS 2010); presentation of the work [C4]. <br />
<br />
Participation at the conference: European Workshop on Heterostructure Technology (HETECH 2010); presentation of the work [C5]. <br />
<br />
Participation at the conference: 23rd International Conference on Indium Phosphide and Related Materials (IPRM 2011): presentation of the works [C6] and [C7].<br />
<br />
<br />
----<br />
<br />
DISMI - Dipartimento di Scienze e Metodi dell'Ingegneria<br />
<br />
Università di Modena e Reggio Emilia<br />
<br />
Pad. Tamburini - Via Amendola 2<br />
<br />
42122, Reggio Emilia<br />
<br />
<br />
mail: luca.morassi@unimore.it<br />
<br />
Tel: +39-0522522638<br />
<br />
Fax: +39-0522522609<br />
<br />
Cell: +39-3381468756</div>83667https://web.ing.unimo.it/wiki/index.php?title=Luca_Morassi&diff=8557Luca Morassi2012-03-28T10:51:47Z<p>83667: </p>
<hr />
<div>[[File:MyPic.JPG|200px|left]]Ph.D. Student<br />
<br />
Course: Electronics and Telecommunications<br />
<br />
----<br />
Brief CV:<br />
<br />
Luca Morassi was born in Mirandola (Mo), Italy, on September 15th, 1982.<br />
<br />
From July 2008 to February 2009 he was in IMEC (Interuniversity MicroElectronics Centre, Leuven, Belgium) for an internship; during this period he worked on the characterization of High-k-based composed stack for MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) gate oxide. In 2009 he received his academic master degree in Electronic Engineering from University of Modena e Reggio Emilia, Italy - Topic: "Characterization and Simulation of High-k Dielectrics for Innovative Non-Volatile Memories". During 2009 he collaborated with University of Modena and Reggio Emilia with a research activity focused on the electrical characterization of high-k material for Non-Volatile Memory (NVM) devices. Since 2010 he is a PhD student at ICT Electronics & Telecommunications Doctorate School, Modena, Italy with a research activity based on III-V compound semiconductor. His main research field is the characterization of InGaAs-channel MOSFETs and MOSHEMTs (Metal Oxide Semiconductor High Electron Mobilty Transistors) for high power and logic applications.<br />
<br />
<br />
----<br />
<br />
List of publications in journals:<br />
<br />
[J1] Padovani, A.; '''Morassi, L.'''; Raghavan, N.; Larcher, L.; Wenhu Liu; Kin Leong Pey; Bersuker, G.; , "A Physical Model for Post-Breakdown Digital Gate Current Noise," Electron Device Letters, IEEE , vol.31, no.9, pp.1032-1034, Sept. 2010<br />
<br />
[J2] '''Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Injo Ok; Bersuker, G.; , "Interface-Trap Effects in Inversion-Type Enhancement-Mode N-Channel MOSFETs," Electron Devices, IEEE Transactions on , vol.58, no.1, pp.107-114, Jan. 2011<br />
<br />
[J3] Bersuker, G.; Veksler, D.; Young, C.D.; Park, H.; Taylor, W.; Kirsch, P.; Jammy, R.; ''' Morassi, L.'''; Padovani, A.; Larcher, L.; “Connecting electrical and structural dielectric characteristics,” International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011<br />
<br />
[J4] '''Morassi, L.'''; Verzellesi, G.; Zhao, H.; Lee, J. C.; Veksler, D.; Bersuker, G.; , "Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs," Electron Devices, IEEE Transactions on , vol.59, no.4, pp.1068-1075, April 2012<br />
<br />
<br />
----<br />
<br />
List of publications in international conferences:<br />
<br />
[C1] '''Morassi, L.'''; Larcher, L.; Pantisano, L.; Padovani, A.; Degreave, R.; Zahid, M. B.; O'Sullivan, B. J.; , "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing," 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009<br />
<br />
[C2] Bersuker, G.; Heh, D.; Young, C.D.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Yew, K.S.; Ong, Y.C.; Ang, D.S.; Pey, K.L.; Taylor, W.; , "Mechanism of high-k dielectric-induced breakdown of the interfacial SiO2 layer," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.373-378, 2-6 May 2010<br />
<br />
[C3] Bersuker, G.; Veksler, D.; Young, C. D.; Park, H.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Taylor, W.; Kirsch, P. D.; Jammy, R.; , "Connecting electrical and structural dielectric characteristics," Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009<br />
<br />
[C4] '''Morassi, L.'''; Verzellesi, G.; Padovani, A.; Larcher, L.; Pavan, P.; Veksler, D.; Injo Ok; Bersuker, G.; , "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.532-535, 2-6 May 2010<br />
<br />
[C5] ''' Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Ok, I.; Bersuker, G.; , “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010<br />
<br />
[C6] '''Morassi, L.'''; Verzellesi, G.; Pavan, P.; Veksler, D.; Ok, I.; Han Zhao; Lee, J.C.; Bersuker, G.; , "Experimental/numerical investigation of buried-channel InGaA MOS-HEMTs with Al2O3 gate dielectric," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C7] '''Morassi, L.'''; Verzellesi, G.; Larcher, L.; Han Zhao; Lee, J.C.; , "Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
<br />
----<br />
<br />
Scientific activities:<br />
<br />
Participation at the conference: IEEE International Reliability Physics Symposium (IRPS 2010); presentation of the work [C4]. <br />
<br />
Participation at the conference: European Workshop on Heterostructure Technology (HETECH 2010); presentation of the work [C5]. <br />
<br />
Participation at the conference: 23rd International Conference on Indium Phosphide and Related Materials (IPRM 2011): presentation of the works [C6] and [C7].<br />
<br />
<br />
----<br />
<br />
DISMI - Dipartimento di Scienze e Metodi dell'Ingegneria<br />
<br />
Università di Modena e Reggio Emilia<br />
<br />
Pad. Tamburini - Via Amendola 2<br />
<br />
42122, Reggio Emilia<br />
<br />
<br />
mail: luca.morassi@unimore.it<br />
<br />
Tel: +39-0522522638<br />
<br />
Fax: +39-0522522609<br />
<br />
Cell: +39-3381468756</div>83667https://web.ing.unimo.it/wiki/index.php?title=Luca_Morassi&diff=8556Luca Morassi2012-03-28T10:45:44Z<p>83667: </p>
<hr />
<div>[[File:MyPic.JPG|200px|left]]Ph.D. Student<br />
<br />
Course: Electronics and Telecommunications<br />
<br />
----<br />
Brief CV:<br />
<br />
Luca Morassi was born in Mirandola (Mo), Italy, on September 15th, 1982.<br />
<br />
From July 2008 to February 2009 he was in IMEC (Interuniversity MicroElectronics Centre, Leuven, Belgium) for an internship; during this period he worked on the characterization of High-k-based composed stack for MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) gate oxide. In 2009 he received his academic master degree in Electronic Engineering from University of Modena e Reggio Emilia, Italy - Topic: "Characterization and Simulation of High-k Dielectrics for Innovative Non-Volatile Memories". During 2009 he collaborated with University of Modena and Reggio Emilia with a research activity focused on the electrical characterization of high-k material for Non-Volatile Memory (NVM) devices. Since 2010 he is a PhD student at ICT Electronics & Telecommunications Doctorate School, Modena, Italy with a research activity based on III-V compound semiconductor. His main research field is the characterization of InGaAs-channel MOSFETs and MOSHEMTs (Metal Oxide Semiconductor High Electron Mobilty Transistors) for high power and logic applications.<br />
<br />
<br />
----<br />
<br />
List of publications in journals:<br />
<br />
[J1] Padovani, A.; '''Morassi, L.'''; Raghavan, N.; Larcher, L.; Wenhu Liu; Kin Leong Pey; Bersuker, G.; , "A Physical Model for Post-Breakdown Digital Gate Current Noise," Electron Device Letters, IEEE , vol.31, no.9, pp.1032-1034, Sept. 2010<br />
<br />
[J2] '''Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Injo Ok; Bersuker, G.; , "Interface-Trap Effects in Inversion-Type Enhancement-Mode N-Channel MOSFETs," Electron Devices, IEEE Transactions on , vol.58, no.1, pp.107-114, Jan. 2011<br />
<br />
[J3] Bersuker, G.; Veksler, D.; Young, C.D.; Park, H.; Taylor, W.; Kirsch, P.; Jammy, R.; , ''' Morassi, L.'''; Padovani, A.; Larcher, L.; “Connecting electrical and structural dielectric characteristics,” International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011<br />
<br />
[J4] '''Morassi, L.'''; Verzellesi, G.; Zhao, H.; Lee, J. C.; Veksler, D.; Bersuker, G.; , "Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs," Electron Devices, IEEE Transactions on , vol.59, no.4, pp.1068-1075, April 2012<br />
<br />
<br />
----<br />
<br />
List of publications in international conferences:<br />
<br />
[C1] '''Morassi, L.'''; Larcher, L.; Pantisano, L.; Padovani, A.; Degreave, R.; Zahid, M. B.; O'Sullivan, B. J.; , "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing," 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009<br />
<br />
[C2] Bersuker, G.; Heh, D.; Young, C.D.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Yew, K.S.; Ong, Y.C.; Ang, D.S.; Pey, K.L.; Taylor, W.; , "Mechanism of high-k dielectric-induced breakdown of the interfacial SiO2 layer," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.373-378, 2-6 May 2010<br />
<br />
[C3] Bersuker, G.; Veksler, D.; Young, C. D.; Park, H.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Taylor, W.; Kirsch, P. D.; Jammy, R.; , "Connecting electrical and structural dielectric characteristics," Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009<br />
<br />
[C4] '''Morassi, L.'''; Verzellesi, G.; Padovani, A.; Larcher, L.; Pavan, P.; Veksler, D.; Injo Ok; Bersuker, G.; , "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.532-535, 2-6 May 2010<br />
<br />
[C5] ''' Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Ok, I.; Bersuker, G.; , “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010<br />
<br />
[C6] '''Morassi, L.'''; Verzellesi, G.; Pavan, P.; Veksler, D.; Ok, I.; Han Zhao; Lee, J.C.; Bersuker, G.; , "Experimental/numerical investigation of buried-channel InGaA MOS-HEMTs with Al2O3 gate dielectric," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C7] '''Morassi, L.'''; Verzellesi, G.; Larcher, L.; Han Zhao; Lee, J.C.; , "Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
<br />
----<br />
<br />
Scientific activities:<br />
<br />
Participation at the conference: IEEE International Reliability Physics Symposium (IRPS 2010); presentation of the work [C4]. <br />
<br />
Participation at the conference: European Workshop on Heterostructure Technology (HETECH 2010); presentation of the work [C5]. <br />
<br />
Participation at the conference: 23rd International Conference on Indium Phosphide and Related Materials (IPRM 2011): presentation of the works [C6] and [C7].<br />
<br />
<br />
----<br />
<br />
DISMI - Dipartimento di Scienze e Metodi dell'Ingegneria<br />
<br />
Università di Modena e Reggio Emilia<br />
<br />
Pad. Tamburini - Via Amendola 2<br />
<br />
42122, Reggio Emilia<br />
<br />
<br />
mail: luca.morassi@unimore.it<br />
<br />
Tel: +39-0522522638<br />
<br />
Fax: +39-0522522609<br />
<br />
Cell: +39-3381468756</div>83667https://web.ing.unimo.it/wiki/index.php?title=Luca_Morassi&diff=8555Luca Morassi2012-03-28T10:42:11Z<p>83667: </p>
<hr />
<div>[[File:MyPic.JPG|200px|left]]Ph.D. Student<br />
<br />
Course: Electronics and Telecommunications<br />
<br />
----<br />
Brief CV:<br />
<br />
Luca Morassi was born in Mirandola (Mo), Italy, on September 15th, 1982.<br />
<br />
From July 2008 to February 2009 he was in IMEC (Interuniversity MicroElectronics Centre, Leuven, Belgium) for an internship; during this period he worked on the characterization of High-k-based composed stack for MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) gate oxide. In 2009 he received his academic master degree in Electronic Engineering from University of Modena e Reggio Emilia, Italy - Topic: "Characterization and Simulation of High-k Dielectrics for Innovative Non-Volatile Memories". During 2009 he collaborated with University of Modena and Reggio Emilia with a research activity focused on the electrical characterization of high-k material for Non-Volatile Memory (NVM) devices. Since 2010 he is a PhD student at ICT Electronics & Telecommunications Doctorate School, Modena, Italy with a research activity based on III-V compound semiconductor. His main research field is the characterization of InGaAs-channel MOSFETs and MOSHEMTs (Metal Oxide Semiconductor High Electron Mobilty Transistors) for high power and logic applications.<br />
<br />
<br />
----<br />
<br />
List of publications in journals:<br />
<br />
[J1] Padovani, A.; '''Morassi, L.'''; Raghavan, N.; Larcher, L.; Wenhu Liu; Kin Leong Pey; Bersuker, G.; , "A Physical Model for Post-Breakdown Digital Gate Current Noise," Electron Device Letters, IEEE , vol.31, no.9, pp.1032-1034, Sept. 2010<br />
<br />
[J2] '''Morassi, L.'''; Padovani, A.; Verzellesi, G.; Veksler, D.; Injo Ok; Bersuker, G.; , "Interface-Trap Effects in Inversion-Type Enhancement-Mode N-Channel MOSFETs," Electron Devices, IEEE Transactions on , vol.58, no.1, pp.107-114, Jan. 2011<br />
<br />
[J3] Bersuker, G.; Veksler, D.; Young, C.D.; Park, H.; Taylor, W.; Kirsch, P.; Jammy, R.; ''' Morassi, L.'''; Padovani, A.; Larcher, L.; “Connecting electrical and structural dielectric characteristics,” International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011<br />
<br />
[J4] '''Morassi, L.'''; Verzellesi, G.; Zhao, H.; Lee, J. C.; Veksler, D.; Bersuker, G.; , "Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs," Electron Devices, IEEE Transactions on , vol.59, no.4, pp.1068-1075, April 2012<br />
<br />
<br />
----<br />
<br />
List of publications in international conferences:<br />
<br />
[C1] '''Morassi, L.'''; Larcher, L.; Pantisano, L.; Padovani, A.; Degreave, R.; Zahid, M. B.; O'Sullivan, B. J.; "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing," 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009<br />
<br />
[C2] Bersuker, G.; Heh, D.; Young, C.D.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Yew, K.S.; Ong, Y.C.; Ang, D.S.; Pey, K.L.; Taylor, W.; , "Mechanism of high-k dielectric-induced breakdown of the interfacial SiO2 layer," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.373-378, 2-6 May 2010<br />
<br />
[C3] Bersuker, G.; Veksler, D.; Young, C. D.; Park, H.; '''Morassi, L.'''; Padovani, A.; Larcher, L.; Taylor, W.; Kirsch, P. D.; Jammy, R.; "Connecting electrical and structural dielectric characteristics," Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009<br />
<br />
[C4] '''Morassi, L.'''; Verzellesi, G.; Padovani, A.; Larcher, L.; Pavan, P.; Veksler, D.; Injo Ok; Bersuker, G.; , "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs," Reliability Physics Symposium (IRPS), 2010 IEEE International , vol., no., pp.532-535, 2-6 May 2010<br />
<br />
[C5] '''L. Morassi''', A. Padovani, G. Verzellesi, D. Veksler, I. Ok and G. Bersuker, “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010<br />
<br />
[C6] '''Morassi, L.'''; Verzellesi, G.; Pavan, P.; Veksler, D.; Ok, I.; Han Zhao; Lee, J.C.; Bersuker, G.; , "Experimental/numerical investigation of buried-channel InGaA MOS-HEMTs with Al2O3 gate dielectric," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
[C7] '''Morassi, L.'''; Verzellesi, G.; Larcher, L.; Han Zhao; Lee, J.C.; , "Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs," Compound Semiconductor Week (CSW/IPRM), 2011 and 23rd International Conference on Indium Phosphide and Related Materials , vol., no., pp.1-3, 22-26 May 2011<br />
<br />
<br />
----<br />
<br />
Scientific activities:<br />
<br />
Participation at the conference: IEEE International Reliability Physics Symposium (IRPS 2010); presentation of the work [C4]. <br />
<br />
Participation at the conference: European Workshop on Heterostructure Technology (HETECH 2010); presentation of the work [C5]. <br />
<br />
Participation at the conference: 23rd International Conference on Indium Phosphide and Related Materials (IPRM 2011): presentation of the works [C6] and [C7].<br />
<br />
<br />
----<br />
<br />
DISMI - Dipartimento di Scienze e Metodi dell'Ingegneria<br />
<br />
Università di Modena e Reggio Emilia<br />
<br />
Pad. Tamburini - Via Amendola 2<br />
<br />
42122, Reggio Emilia<br />
<br />
<br />
mail: luca.morassi@unimore.it<br />
<br />
Tel: +39-0522522638<br />
<br />
Fax: +39-0522522609<br />
<br />
Cell: +39-3381468756</div>83667https://web.ing.unimo.it/wiki/index.php?title=Luca_Morassi&diff=8554Luca Morassi2012-03-28T10:28:18Z<p>83667: </p>
<hr />
<div>[[File:MyPic.JPG|200px|left]]Ph.D. Student<br />
<br />
Course: Electronics and Telecommunications<br />
<br />
----<br />
Brief CV:<br />
<br />
Luca Morassi was born in Mirandola (Mo), Italy, on September 15th, 1982.<br />
<br />
From July 2008 to February 2009 he was in IMEC (Interuniversity MicroElectronics Centre, Leuven, Belgium) for an internship; during this period he worked on the characterization of High-k-based composed stack for MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) gate oxide. In 2009 he received his academic master degree in Electronic Engineering from University of Modena e Reggio Emilia, Italy - Topic: "Characterization and Simulation of High-k Dielectrics for Innovative Non-Volatile Memories". During 2009 he collaborated with University of Modena and Reggio Emilia with a research activity focused on the electrical characterization of high-k material for Non-Volatile Memory (NVM) devices. Since 2010 he is a PhD student at ICT Electronics & Telecommunications Doctorate School, Modena, Italy with a research activity based on III-V compound semiconductor. His main research field is the characterization of InGaAs-channel MOSFETs and MOSHEMTs (Metal Oxide Semiconductor High Electron Mobilty Transistors) for high power and logic applications.<br />
<br />
<br />
----<br />
<br />
List of publications in journals:<br />
<br />
[J1] A. Padovani, '''L. Morassi''', N. Raghavan, L. Larcher, L. Wenhu, K. L. Pey, and G. Bersuker, "A Physical Model for Post-Breakdown Digital Gate Current Noise", IEEE Electron Device Letters, vol. 31, no. 9, pp.1032-1034, Sep. 2010.<br />
<br />
[J2] '''L. Morassi''', A. Padovani, G. Verzellesi, D. Veksler, I. Ok, G. Bersuker, "Interface-Trap Effects in Inversion-Type Enhancement-Mode InGaAs/ZrO2 N-Channel MOSFETs", IEEE Transactions on Electron Devices, vol. 58, no. 1, pp.107-114, Jan. 2011.<br />
<br />
[J3] G. Bersuker, D. Veksler, C. D. Young, H. Park, W. Taylor, P. Kirsch, R, Jammy, '''L. Morassi''', A. Padovani, and L. Larcher, “Connecting electrical and structural dielectric characteristics”, International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011.<br />
<br />
[J4] '''Morassi, L.'''; Verzellesi, G.; Zhao, H.; Lee, J. C.; Veksler, D.; Bersuker, G.; , "Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs," Electron Devices, IEEE Transactions on , vol.59, no.4, pp.1068-1075, April 2012<br />
<br />
<br />
----<br />
<br />
List of publications in international conferences:<br />
<br />
[C1] '''L. Morassi''', L. Larcher, L. Pantisano, A. Padovani, R. Degreave, M. B. Zahid, and B. J. O'Sullivan, "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing", 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009.<br />
<br />
[C2] G. Bersuker, D. Heh, C. D. Young, '''L. Morassi''', A. Padovani, L. Larcher, K. S. Yew, Y. C. Ong, D. S. Ang, K. L. Pey, and W. Taylor, "Mechanism of high-k dielectric-induced breakdown of interfacial SiO2 layer", IEEE International Reliability Physics Symposium, Anaheim (CA), USA, May 2-6, 2010, pp. 373-378.<br />
<br />
[C3] G. Bersuker, D. Veksler, C. D. Young, H. Park, '''L. Morassi''', A. Padovani, L. Larcher, W. Taylor, P. D. Kirsch, and R. Jammy, "Connecting electrical and structural dielectric characteristics", Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009.<br />
<br />
[C4] '''L. Morassi''', G. Verzellesi, A. Padovani, L. Larcher, P. Pavan, D. Veksler, I. Ok, and G. Bersuker, "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs", IEEE International Reliability Physics Symposium, Anaheim (CA), USA, May 2-6, 2010, pp. 532-535.<br />
<br />
[C5] '''L. Morassi''', A. Padovani, G. Verzellesi, D. Veksler, I. Ok and G. Bersuker, “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010.<br />
<br />
[C6] '''L. Morassi''', G. Verzellesi, P. Pavan, D. Veksler, I. Ok, H. Zhao, J. C. Lee and G. Bersuker, “Experimental/numerical investigation of buried-channel InGaA MOS-HEMTs with Al2O3 gate dielectric”, 23rd International Conference on Indium Phosphide and Related Materials (IPRM2011), Berlin, Germany, May 22-26, 2011, pp. 103-105.<br />
<br />
[C7] '''L. Morassi''', G. Verzellesi, L. Larcher, I. Ok, H. Zhao and J. C. Lee, “Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs”, 23rd International Conference on Indium Phosphide and Related Materials (IPRM2011), Berlin, Germany, May 22-26, 2011, pp. 327-329.<br />
<br />
<br />
----<br />
<br />
Scientific activities:<br />
<br />
Participation at the conference: IEEE International Reliability Physics Symposium (IRPS 2010); presentation of the work [C4]. <br />
<br />
Participation at the conference: European Workshop on Heterostructure Technology (HETECH 2010); presentation of the work [C5]. <br />
<br />
Participation at the conference: 23rd International Conference on Indium Phosphide and Related Materials (IPRM 2011): presentation of the works [C6] and [C7].<br />
<br />
<br />
----<br />
<br />
DISMI - Dipartimento di Scienze e Metodi dell'Ingegneria<br />
<br />
Università di Modena e Reggio Emilia<br />
<br />
Pad. Tamburini - Via Amendola 2<br />
<br />
42122, Reggio Emilia<br />
<br />
<br />
mail: luca.morassi@unimore.it<br />
<br />
Tel: +39-0522522638<br />
<br />
Fax: +39-0522522609<br />
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Cell: +39-3381468756</div>83667https://web.ing.unimo.it/wiki/index.php?title=Luca_Morassi&diff=8553Luca Morassi2012-03-28T10:27:40Z<p>83667: </p>
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<div>[[File:MyPic.JPG|200px|left]]Ph.D. Student<br />
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Course: Electronics and Telecommunications<br />
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Brief CV:<br />
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Luca Morassi was born in Mirandola (Mo), Italy, on September 15th, 1982.<br />
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From July 2008 to February 2009 he was in IMEC (Interuniversity MicroElectronics Centre, Leuven, Belgium) for an internship; during this period he worked on the characterization of High-k-based composed stack for MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) gate oxide. In 2009 he received his academic master degree in Electronic Engineering from University of Modena e Reggio Emilia, Italy - Topic: "Characterization and Simulation of High-k Dielectrics for Innovative Non-Volatile Memories". During 2009 he collaborated with University of Modena and Reggio Emilia with a research activity focused on the electrical characterization of high-k material for Non-Volatile Memory (NVM) devices. Since 2010 he is a PhD student at ICT Electronics & Telecommunications Doctorate School, Modena, Italy with a research activity based on III-V compound semiconductor. His main research field is the characterization of InGaAs-channel MOSFETs and MOSHEMTs (Metal Oxide Semiconductor High Electron Mobilty Transistors) for high power and logic applications.<br />
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List of publications in journals:<br />
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[J1] A. Padovani, '''L. Morassi''', N. Raghavan, L. Larcher, L. Wenhu, K. L. Pey, and G. Bersuker, "A Physical Model for Post-Breakdown Digital Gate Current Noise", IEEE Electron Device Letters, vol. 31, no. 9, pp.1032-1034, Sep. 2010.<br />
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[J2] '''L. Morassi''', A. Padovani, G. Verzellesi, D. Veksler, I. Ok, G. Bersuker, "Interface-Trap Effects in Inversion-Type Enhancement-Mode InGaAs/ZrO2 N-Channel MOSFETs", IEEE Transactions on Electron Devices, vol. 58, no. 1, pp.107-114, Jan. 2011.<br />
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[J3] G. Bersuker, D. Veksler, C. D. Young, H. Park, W. Taylor, P. Kirsch, R, Jammy, '''L. Morassi''', A. Padovani, and L. Larcher, “Connecting electrical and structural dielectric characteristics”, International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011.<br />
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[J4] "Morassi, L."; Verzellesi, G.; Zhao, H.; Lee, J. C.; Veksler, D.; Bersuker, G.; , "Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs," Electron Devices, IEEE Transactions on , vol.59, no.4, pp.1068-1075, April 2012<br />
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List of publications in international conferences:<br />
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[C1] '''L. Morassi''', L. Larcher, L. Pantisano, A. Padovani, R. Degreave, M. B. Zahid, and B. J. O'Sullivan, "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing", 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009.<br />
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[C2] G. Bersuker, D. Heh, C. D. Young, '''L. Morassi''', A. Padovani, L. Larcher, K. S. Yew, Y. C. Ong, D. S. Ang, K. L. Pey, and W. Taylor, "Mechanism of high-k dielectric-induced breakdown of interfacial SiO2 layer", IEEE International Reliability Physics Symposium, Anaheim (CA), USA, May 2-6, 2010, pp. 373-378.<br />
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[C3] G. Bersuker, D. Veksler, C. D. Young, H. Park, '''L. Morassi''', A. Padovani, L. Larcher, W. Taylor, P. D. Kirsch, and R. Jammy, "Connecting electrical and structural dielectric characteristics", Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009.<br />
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[C4] '''L. Morassi''', G. Verzellesi, A. Padovani, L. Larcher, P. Pavan, D. Veksler, I. Ok, and G. Bersuker, "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs", IEEE International Reliability Physics Symposium, Anaheim (CA), USA, May 2-6, 2010, pp. 532-535.<br />
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[C5] '''L. Morassi''', A. Padovani, G. Verzellesi, D. Veksler, I. Ok and G. Bersuker, “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010.<br />
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[C6] '''L. Morassi''', G. Verzellesi, P. Pavan, D. Veksler, I. Ok, H. Zhao, J. C. Lee and G. Bersuker, “Experimental/numerical investigation of buried-channel InGaA MOS-HEMTs with Al2O3 gate dielectric”, 23rd International Conference on Indium Phosphide and Related Materials (IPRM2011), Berlin, Germany, May 22-26, 2011, pp. 103-105.<br />
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[C7] '''L. Morassi''', G. Verzellesi, L. Larcher, I. Ok, H. Zhao and J. C. Lee, “Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs”, 23rd International Conference on Indium Phosphide and Related Materials (IPRM2011), Berlin, Germany, May 22-26, 2011, pp. 327-329.<br />
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Scientific activities:<br />
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Participation at the conference: IEEE International Reliability Physics Symposium (IRPS 2010); presentation of the work [C4]. <br />
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Participation at the conference: European Workshop on Heterostructure Technology (HETECH 2010); presentation of the work [C5]. <br />
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Participation at the conference: 23rd International Conference on Indium Phosphide and Related Materials (IPRM 2011): presentation of the works [C6] and [C7].<br />
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DISMI - Dipartimento di Scienze e Metodi dell'Ingegneria<br />
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Università di Modena e Reggio Emilia<br />
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Pad. Tamburini - Via Amendola 2<br />
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42122, Reggio Emilia<br />
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mail: luca.morassi@unimore.it<br />
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Tel: +39-0522522638<br />
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Fax: +39-0522522609<br />
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Cell: +39-3381468756</div>83667