Difference between revisions of "Luca Morassi"

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List of publications and papers in international conferences:
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List of publications in journals:
  
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[J1] A. Padovani, '''L. Morassi''', N. Raghavan, L. Larcher, L. Wenhu, K. L. Pey, and G. Bersuker, "A Physical Model for Post-Breakdown Digital Gate Current Noise", IEEE Electron Device Letters, vol. 31, no. 9, pp.1032-1034, Sep. 2010.
  
A. Padovani, '''L. Morassi''', N. Raghavan, L. Larcher, L. Wenhu, K. L. Pey, and G. Bersuker, "A Physical Model for Post-Breakdown Digital Gate Current Noise", IEEE Electron Device Letters, vol. 31, no. 9, pp.1032-1034, Sep. 2010.
+
[J2] '''L. Morassi''', A. Padovani, G. Verzellesi, D. Veksler, I. Ok, G. Bersuker, "Interface-Trap Effects in Inversion-Type Enhancement-Mode InGaAs/ZrO2 N-Channel MOSFETs", IEEE Transactions on Electron Devices, vol. 58, no. 1, pp.107-114, Jan. 2011.
  
'''L. Morassi''', L. Larcher, L. Pantisano, A. Padovani, R. Degreave, M. B. Zahid, and B. J. O'Sullivan, "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing", 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009.
+
[J3] G. Bersuker, D. Veksler, C. D. Young, H. Park, W. Taylor, P. Kirsch, R, Jammy, '''L. Morassi''', A. Padovani, and L. Larcher, “Connecting electrical and structural dielectric characteristics”, International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011.
  
G. Bersuker, D. Heh, C. D. Young, '''L. Morassi''', A. Padovani, L. Larcher, K. S. Yew, Y. C. Ong, D. S. Ang, K. L. Pey, and W. Taylor, "Mechanism of high-k dielectric-induced breakdown of interfacial SiO2 layer", IEEE International Reliability Physics Symposium, Anaheim (CA), USA, May 2-6, 2010, pp. 373-378.
+
List of publications in international conferences:
  
G. Bersuker, D. Veksler, C. D. Young, H. Park, '''L. Morassi''', A. Padovani, L. Larcher, W. Taylor, P. D. Kirsch, and R. Jammy, "Connecting electrical and structural dielectric characteristics", Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009.
+
[C1] '''L. Morassi''', L. Larcher, L. Pantisano, A. Padovani, R. Degreave, M. B. Zahid, and B. J. O'Sullivan, "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing", 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009.
  
'''L. Morassi''', G. Verzellesi, A. Padovani, L. Larcher, P. Pavan, D. Veksler, I. Ok, and G. Bersuker, "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs", IEEE International Reliability Physics Symposium, Anaheim (CA), USA, May 2-6, 2010, pp. 532-535.
+
[C2] G. Bersuker, D. Heh, C. D. Young, '''L. Morassi''', A. Padovani, L. Larcher, K. S. Yew, Y. C. Ong, D. S. Ang, K. L. Pey, and W. Taylor, "Mechanism of high-k dielectric-induced breakdown of interfacial SiO2 layer", IEEE International Reliability Physics Symposium, Anaheim (CA), USA, May 2-6, 2010, pp. 373-378.
  
'''L. Morassi''', A. Padovani, G. Verzellesi, D. Veksler, I. Ok and G. Bersuker, “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010.
+
[C3] G. Bersuker, D. Veksler, C. D. Young, H. Park, '''L. Morassi''', A. Padovani, L. Larcher, W. Taylor, P. D. Kirsch, and R. Jammy, "Connecting electrical and structural dielectric characteristics", Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009.
  
'''L. Morassi''', A. Padovani, G. Verzellesi, D. Veksler, I. Ok, G. Bersuker, "Interface-Trap Effects in Inversion-Type Enhancement-Mode InGaAs/ZrO2 N-Channel MOSFETs", IEEE Transactions on Electron Devices, vol. 58, no. 1, pp.107-114, Jan. 2011.
+
[C4] '''L. Morassi''', G. Verzellesi, A. Padovani, L. Larcher, P. Pavan, D. Veksler, I. Ok, and G. Bersuker, "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs", IEEE International Reliability Physics Symposium, Anaheim (CA), USA, May 2-6, 2010, pp. 532-535.
  
G. Bersuker, D. Veksler, C. D. Young, H. Park, W. Taylor, P. Kirsch, R, Jammy, '''L. Morassi''', A. Padovani, and L. Larcher, “Connecting electrical and structural dielectric characteristics”, International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011.
+
[C5] '''L. Morassi''', A. Padovani, G. Verzellesi, D. Veksler, I. Ok and G. Bersuker, “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010.
 +
 
 +
[C6] '''L. Morassi''', G. Verzellesi, P. Pavan, D. Veksler, I. Ok, H. Zhao, J. C. Lee and G. Bersuker, “Experimental/numerical investigation of buried-channel InGaA MOS-HEMTs with Al2O3 gate dielectric”, 23rd International Conference on Indium Phosphide and Related Materials (IPRM2011), Berlin, Germany, May 22-26, 2011, pp. 103-105.
 +
 
 +
[C7] '''L. Morassi''', G. Verzellesi, P. Pavan, I. Ok, H. Zhao and J. C. Lee, “Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs”, 23rd International Conference on Indium Phosphide and Related Materials (IPRM2011), Berlin, Germany, May 22-26, 2011, pp. 327-329.
  
  
Line 38: Line 43:
  
  
Participation at the conference: IEEE International Reliability Physics Symposium; oral presentation of the work:
+
Participation at the conference: IEEE International Reliability Physics Symposium (IRPS 2010); presentation of the work [C4].
 
 
'''L. Morassi''', G. Verzellesi, A. Padovani, L. Larcher, P. Pavan, D. Veksler, I. Ok, and G. Bersuker, "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs", IEEE International Reliability Physics Symposium, Anaheim (CA), USA, May 2-6, 2010, pp. 532-535.
 
  
Participation at the conference: European Workshop on Heterostructure Technology; oral presentation of the work:
+
Participation at the conference: European Workshop on Heterostructure Technology (HETECH 2010); presentation of the work [C5]. 
  
'''L. Morassi''', A. Padovani, G. Verzellesi, D. Veksler, I. Ok and G. Bersuker, “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010.
+
Participation at the conference: 23rd International Conference on Indium Phosphide and Related Materials (IPRM 2011): presentation of the works [C6] and [C7].
  
  

Revision as of 11:34, 1 June 2011

MyPic.JPG

Ph.D. Student

Course: Electronics and Telecommunications


Brief CV:

Luca Morassi was born in Mirandola (Mo), Italy, on September 15th, 1982.

From July 2008 to February 2009 he was in IMEC (Interuniversity MicroElectronics Centre, Leuven, Belgium) for an internship; during this period he worked on the characterization of High-k-based composed stack for MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) gate oxide. In 2009 he received his academic master degree in Electronic Engineering from University of Modena e Reggio Emilia, Italy - Topic: "Characterization and Simulation of High-k Dielectrics for Innovative Non-Volatile Memories". During 2009 he collaborated with University of Modena and Reggio Emilia with a research activity focused on the electrical characterization of high-k material for Non-Volatile Memory (NVM) devices. Since 2010 he is a PhD student at ICT Electronics & Telecommunications Doctorate School, Modena, Italy with a research activity based on III-V compound semiconductor. His main research field is the characterization of InGaAs-channel MOSFETs and MOSHEMTs (Metal Oxide Semiconductor High Electron Mobilty Transistors) for high power and logic applications.



List of publications in journals:

[J1] A. Padovani, L. Morassi, N. Raghavan, L. Larcher, L. Wenhu, K. L. Pey, and G. Bersuker, "A Physical Model for Post-Breakdown Digital Gate Current Noise", IEEE Electron Device Letters, vol. 31, no. 9, pp.1032-1034, Sep. 2010.

[J2] L. Morassi, A. Padovani, G. Verzellesi, D. Veksler, I. Ok, G. Bersuker, "Interface-Trap Effects in Inversion-Type Enhancement-Mode InGaAs/ZrO2 N-Channel MOSFETs", IEEE Transactions on Electron Devices, vol. 58, no. 1, pp.107-114, Jan. 2011.

[J3] G. Bersuker, D. Veksler, C. D. Young, H. Park, W. Taylor, P. Kirsch, R, Jammy, L. Morassi, A. Padovani, and L. Larcher, “Connecting electrical and structural dielectric characteristics”, International Journal of High Speed Electronics and Systems (IJHSES), vol. 20(1), pp. 65-79, 2011.

List of publications in international conferences:

[C1] L. Morassi, L. Larcher, L. Pantisano, A. Padovani, R. Degreave, M. B. Zahid, and B. J. O'Sullivan, "Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing", 41th International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, 2009.

[C2] G. Bersuker, D. Heh, C. D. Young, L. Morassi, A. Padovani, L. Larcher, K. S. Yew, Y. C. Ong, D. S. Ang, K. L. Pey, and W. Taylor, "Mechanism of high-k dielectric-induced breakdown of interfacial SiO2 layer", IEEE International Reliability Physics Symposium, Anaheim (CA), USA, May 2-6, 2010, pp. 373-378.

[C3] G. Bersuker, D. Veksler, C. D. Young, H. Park, L. Morassi, A. Padovani, L. Larcher, W. Taylor, P. D. Kirsch, and R. Jammy, "Connecting electrical and structural dielectric characteristics", Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico, Dec. 13-16, 2009.

[C4] L. Morassi, G. Verzellesi, A. Padovani, L. Larcher, P. Pavan, D. Veksler, I. Ok, and G. Bersuker, "Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs", IEEE International Reliability Physics Symposium, Anaheim (CA), USA, May 2-6, 2010, pp. 532-535.

[C5] L. Morassi, A. Padovani, G. Verzellesi, D. Veksler, I. Ok and G. Bersuker, “Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics”, 19th European Workshop on Heterostructure Technology (HETEC2010), Crete, Greece, Oct. 18-20, 2010.

[C6] L. Morassi, G. Verzellesi, P. Pavan, D. Veksler, I. Ok, H. Zhao, J. C. Lee and G. Bersuker, “Experimental/numerical investigation of buried-channel InGaA MOS-HEMTs with Al2O3 gate dielectric”, 23rd International Conference on Indium Phosphide and Related Materials (IPRM2011), Berlin, Germany, May 22-26, 2011, pp. 103-105.

[C7] L. Morassi, G. Verzellesi, P. Pavan, I. Ok, H. Zhao and J. C. Lee, “Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs”, 23rd International Conference on Indium Phosphide and Related Materials (IPRM2011), Berlin, Germany, May 22-26, 2011, pp. 327-329.



Scientific activities:


Participation at the conference: IEEE International Reliability Physics Symposium (IRPS 2010); presentation of the work [C4].

Participation at the conference: European Workshop on Heterostructure Technology (HETECH 2010); presentation of the work [C5].

Participation at the conference: 23rd International Conference on Indium Phosphide and Related Materials (IPRM 2011): presentation of the works [C6] and [C7].



DISMI - Dipartimento di Scienze e Metodi dell'Ingegneria

Università di Modena e Reggio Emilia

Pad. Tamburini - Via Amendola 2

42122, Reggio Emilia


mail: luca.morassi@unimore.it

Tel: +39-0522522638

Fax: +39-0522522609

Cell: +39-3381468756